Digital Physical Design Engineer


Reporting to the Hardware Engineer Manager and based in the Company's headquarters in Dublin, Ireland, the DIGITAL PHYSICAL DESIGN ENGINEER

  • Is responsible for the physical implementation, going from RTL to GDSII, for all aspects of the digital core from baseband blocks through to full top level and across multiple CMOS nodes
  • Works as part of a cross-functional team to deliver the next generation products from concept to volume production
  • Interact with other engineers in the digital and RF /analog groups to ensure products are delivered to meet or exceed specifications, on time
  • Support concurrent engineering teams to ensure issues with current products are resolved in a timely manner and to ensure their on-going high yield in volume production.


Duties include:

  • Work with project managers to plan digital back end tasks
  • Physically aware digital synthesis at the block, module and top level
  • Work with block and system designers to achieve timing and power closure
  • Floorplanning of digital top-level, including IP hard macros
  • Power grid design with UPF and optimisation with IR drop analysis
  • Clock tree synthesis
  • Place and route 
  • Chip finishing (LVS, DRC, DMF) through to GDSII generation
  • Extraction and static timing signoff
  • ECO flows


Desired Skills and Experience:

  • Extensive experience in the low power digital ASIC backend Design flow on 40nm or lower
  • Experience of the Synopsys physical implementation tool set is a requirement
  • Have been involved in multiple design tape-outs
  • Experience in low power IC design techniques including UPF
  • Experience in the integration of IP hard macros
  • Working knowledge of different scripting languages (C, Perl, Python) would be an advantage
  • Excellent problem solving and analytical skills
  • Excellent communication skills and ability to work on own initiative to come up with innovative solutions
  • At least 5 years of experience in relevant product development